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@celox-sim/celox / index / RunTestOptions

Interface: RunTestOptions ​

Defined in: packages/celox/src/testbench.ts:240

Properties ​

clockType? ​

optional clockType?: "posedge" | "negedge"

Defined in: packages/celox/src/types.ts:337

Clock polarity. Default: "posedge".

Inherited from ​

SimulatorOptions.clockType

components? ​

optional components?: Record<string, InjectedTbComponent>

Defined in: packages/celox/src/testbench.ts:241

craneliftOptLevel? ​

optional craneliftOptLevel?: "none" | "speed" | "speedAndSize"

Defined in: packages/celox/src/types.ts:315

Cranelift backend optimization level. Default: "speed".

Inherited from ​

SimulatorOptions.craneliftOptLevel

deadStorePolicy? ​

optional deadStorePolicy?: "off" | "preserveTopPorts" | "preserveAllPorts"

Defined in: packages/celox/src/types.ts:348

Dead store elimination policy. Default: "off". When optLevel is "O2", defaults to "preserveTopPorts" unless explicitly set.

Inherited from ​

SimulatorOptions.deadStorePolicy

enableAliasAnalysis? ​

optional enableAliasAnalysis?: boolean

Defined in: packages/celox/src/types.ts:326

Enable alias analysis in the Cranelift egraph optimization pass. Default: true. Only effective when craneliftOptLevel is not "none".

Inherited from ​

SimulatorOptions.enableAliasAnalysis

enableVerifier? ​

optional enableVerifier?: boolean

Defined in: packages/celox/src/types.ts:331

Enable the Cranelift IR verifier. Default: true. Disabling saves compile time at the cost of less validation.

Inherited from ​

SimulatorOptions.enableVerifier

extraSource? ​

optional extraSource?: string

Defined in: packages/celox/src/types.ts:341

Additional Veryl source to append to the main source code.

Inherited from ​

SimulatorOptions.extraSource

falseLoops? ​

optional falseLoops?: LoopBreak[]

Defined in: packages/celox/src/types.ts:333

False-loop declarations to ignore during compilation.

Inherited from ​

SimulatorOptions.falseLoops

fourState? ​

optional fourState?: boolean

Defined in: packages/celox/src/types.ts:279

Enable 4-state (X) simulation. Default: false.

Inherited from ​

SimulatorOptions.fourState

optimize? ​

optional optimize?: boolean

Defined in: packages/celox/src/types.ts:308

Shorthand to enable/disable all SIRT optimization passes. true = all on (O1), false = all off (O0). Overridden by optLevel or optimizeOptions if set.

Deprecated ​

Use optLevel instead.

Inherited from ​

SimulatorOptions.optimize

optimizeOptions? ​

optional optimizeOptions?: OptimizeOptions

Defined in: packages/celox/src/types.ts:313

Per-pass SIRT optimizer flags. Takes precedence over optimize.

Deprecated ​

Use optLevel + passOverrides instead.

Inherited from ​

SimulatorOptions.optimizeOptions

optLevel? ​

optional optLevel?: "O0" | "O1" | "O2"

Defined in: packages/celox/src/types.ts:288

Optimization level preset. Default: "O1".

  • "O0": No SIR optimizations (except TailCallSplit). Fast compilation.
  • "O1": All SIR optimizations enabled. Default.
  • "O2": O1 + dead store elimination (PreserveTopPorts).

Inherited from ​

SimulatorOptions.optLevel

parameters? ​

optional parameters?: ParamOverride[]

Defined in: packages/celox/src/types.ts:343

Top-level module parameter overrides.

Inherited from ​

SimulatorOptions.parameters

passOverrides? ​

optional passOverrides?: string[]

Defined in: packages/celox/src/types.ts:301

Per-pass overrides applied on top of optLevel. Each entry: "+sir:<pass_name>" to enable, "-sir:<pass_name>" to disable.

Valid SIR passes: store_load_forwarding, hoist_common_branch_loads, bit_extract_peephole, optimize_blocks, split_wide_commits, commit_sinking, inline_commit_forwarding, eliminate_dead_working_stores, reschedule, coalesce_stores, gvn, concat_folding, xor_chain_folding, vectorize_concat, split_coalesced_stores, partial_forward, identity_store_bypass, tail_call_split

Example ​

ts
["-sir:reschedule", "+sir:gvn"]

Inherited from ​

SimulatorOptions.passOverrides

regallocAlgorithm? ​

optional regallocAlgorithm?: "backtracking" | "singlePass"

Defined in: packages/celox/src/types.ts:321

Register allocator algorithm for the Cranelift backend. Default: "backtracking".

  • "backtracking": Slower compilation but generates better code with fewer spills.
  • "singlePass": Much faster compilation but generates code with more register spills.

Inherited from ​

SimulatorOptions.regallocAlgorithm

resetType? ​

optional resetType?: "async_high" | "async_low" | "sync_high" | "sync_low"

Defined in: packages/celox/src/types.ts:339

Reset type. Default: "async_low".

Inherited from ​

SimulatorOptions.resetType

threads? ​

optional threads?: number

Defined in: packages/celox/src/types.ts:358

Simulation threads, including the calling thread. Default: 1.

With more than one thread, phases with enough independent work get lane-partitioned alternatives that run concurrently; each is kept only when it measures faster than its sequential version. Results are identical to sequential simulation. Use at most the number of physical cores.

Inherited from ​

SimulatorOptions.threads

tier? ​

optional tier?: boolean

Defined in: packages/celox/src/types.ts:369

Run tiered: execution starts on the interpreter immediately while the host's compiled tier is prepared on a background thread, and the simulation adopts it at the next safe point after compilation. Default: false (compile up front before the first tick).

Honored by Simulator.create, fromSource, and fromProject; rejected by fromFrontendArtifact, the time-based Simulation factories, and addons without tiered support (e.g. WASM).

Inherited from ​

SimulatorOptions.tier

trueLoops? ​

optional trueLoops?: TrueLoopSpec[]

Defined in: packages/celox/src/types.ts:335

True-loop declarations with convergence limits.

Inherited from ​

SimulatorOptions.trueLoops

vcd? ​

optional vcd?: string

Defined in: packages/celox/src/types.ts:281

Path to write VCD waveform output.

Inherited from ​

SimulatorOptions.vcd